This invention relates to programmable logic array integrated circuit devices, and more particularly to the manner in which such devices are organized.
Programmable logic array integrated circuit devices are well known, as is shown, for example, by Cliff et al. U.S. Pat. No. 5,260,611 and Cliff et al. U.S. patent application Ser. No. 08/442,795, filed May 17, 1995, both of which are hereby incorporated by reference herein. Typical devices of these general kinds include a plurality of regions of programmable logic, each region being programmable to perform any of a plurality of relatively elementary logic functions on input signals applied to the region. A network of interconnection conductors is also provided on the device for programmably conveying signals to, from, and between the logic regions. By interconnecting the logic regions in various ways, the elementary logic functions performed by the individual regions can be concatenated to perform very complex logic.
The basic logic of the logic regions may be look-up table logic (as is discussed for the most part in the two references mentioned above), product term type logic (as is discussed for the most part in Wong et al. U.S. Pat. No. 4,871,930 (which is also hereby incorporated by reference herein)), or any other suitable type of logic. Any of these technologies may be used in the devices of this invention.
Programmable logic devices are usually intended as general-purpose devices. The designer of the device therefore does not know how much circuitry to provide for interconnecting the logic regions of the device. Some users may require large amounts of interconnection resources, while other users may require smaller amounts of such resources. Although it is theoretically possible to provide completely universal interconnection resources (which would allow any connection to be made no matter what other connections were also required), that is generally regarded as wasteful because only a small fraction of such completely universal interconnection resources are ever likely to be used. Thus one of the problems that the designer of programmable logic devices must deal with is to devise interconnection resources that are sufficient to meet the needs of most probable applications of the device without being wastefully more than will generally be needed. It is also important to avoid requirements for passing signals through large numbers of interconnection elements because such elements tend to slow down signal transmission and therefore reduce the operating speed of the device.
In view of the foregoing, it is an object of his invention to provide improved interconnection resources for programmable logic array integrated circuit devices.
It is a more particular object of the invention to provide interconnection resources for programmable logic array integrated circuit devices that provide a high degree of interconnection flexibility at relatively low cost in terms of "overhead" such as space occupied by interconnection conductors, programmable interconnections and the programmable elements required to control them, etc.